1. Field
Example embodiments relate to an electronic circuit, and for example, to a level converting flip-flop and/or a method of operating the same.
2. Description of Related Art
A level converting flip-flop is a circuit for interfacing circuits having different supply voltages. The level converting flip-flop may be placed between a logic circuit, e.g., a logic controller or a memory included in an integrated circuit (IC), and an input/output circuit inputting or outputting a signal used in the logic circuit. The level converting flip-flop may be used in a write/read circuit of a flash memory, a data path of a thin film transistor (TFT) liquid crystal display (LCD) driver IC, a data path of a low-temperature poly-silicon (LTPS) TFT LCD driver IC, a method of dynamic voltage scaling, and a method of clustered voltage scaling. The method of dynamic voltage scaling and the method of clustered voltage scaling are used for embodying a system consuming less power.
FIG. 1 is a circuit diagram illustrating a conventional level converting flip-flop 100. The conventional level converting flip-flop 100 is a conditionally dischargeable level converting flip-flop. Referring to FIG. 1, the conventional level converting flip-flop 100 converts an input data signal D having an input supply voltage VDDL (for example, 1.5 V) into an output data signal Q having an output supply voltage VDDH (for example, 2.3 V) that is larger than the input supply voltage VDDL, in response to a clock signal CK. The conventional level converting flip-flop 100 generates an inverse signal QB of the output data signal Q.
The conventional level converting flip-flop 100 uses a weak P-channel metal-oxide-semiconductor (PMOS) transistor P1 in order to pull-up a voltage of a node NX. The PMOS transistor P1 has a smaller current-driving capability and pre-charges the node NX as an output supply voltage VDDH.
A pull-up operation of the level converting flip-flop 100 may be explained as follows. If the input data signal D makes a transition from a low level, e.g., a ground voltage VSS, to a high level, e.g., the input supply voltage VDDL, a conflict between the turned-on PMOS transistor P1 and turned-on N-channel metal-oxide-semiconductor (NMOS) transistors N1, N3, N5, and N7 occurs. If the conflict occurs, the output data signal Q makes a transition to a high level, e.g., the output supply voltage VDDH.
A short-circuit current flows through the PMOS transistor P1 and the NMOS transistors N1, N3, N5, and N7 because of the conflict. In order to reduce the amount of short-circuit current, the PMOS transistor P1 may be fabricated to be of a smaller size. However, if a length of a channel and a width of a channel of the PMOS transistor P1 become smaller, a pre-charge speed of the node NX decreases, and the level converting flip-flop 100 may not operate at a higher speed.
During the pull-up operation of the conventional level converting flip-flop 100, the node NX fully swings between an output supply voltage VDDH and a ground voltage VSS. Accordingly, the conventional level converting flip-flop 100 may consume a larger amount of electric power and have a pull-up speed of a smaller output data signal Q.
A pull-up speed of the output data signal Q is determined according to a level of the output supply voltage VDDH and sizes, e.g., channel lengths and widths, of the PMOS transistors P1 and P2. A pull-down speed of the output data signal Q is determined according to a level of the input supply voltage VDDL and the sizes, e.g., channel lengths and widths, of NMOS transistors N2, N4, and N6. Accordingly, a clock-to-output time (e.g., a delay time until the output data signal Q occurs after a clock signal CK is input) may be significantly changed according to changes in the input supply voltage VDDL. A clock-to-output time if the output data signal Q rises to a high level, e.g., the output supply voltage VDDH, and a clock-to-output time if the output data signal Q falls to a low level, e.g., the ground voltage VSS, change according to changes in the output supply voltage VDDH, and a duty ratio of the output data signal Q may significantly change. Accordingly, a propagation delay time of the conventional level converting flip-flop 100 may not be constant because of the changes in the output supply voltage VDDH.
FIG. 2 is a circuit diagram illustrating another conventional level converting flip-flop 200. The conventional level converting flip-flop 200 is a circuit having a flip-flop connected in parallel to a level converter. The conventional level converting flip-flop 200 may be used in a TFT LCD driver IC and a LTPS TFT LCD driver IC. The conventional level converting flip-flop 200 may have a larger circuit area.
Referring to FIG. 2, the conventional level converting flip-flop 200 converts an input data signal D having an input supply voltage VDDL into an output data signal having an output supply voltage VDDH that is larger than the input supply voltage VDDL in response to a clock signal CK.
If the level converting flip-flop 200 performs a pull-up operation or a pull-down operation, a conflict between turned-on PMOS transistors 201 and 203 and a turned-on NMOS transistor 205 or between turned-on PMOS transistors 202 and 204 and a turned-on NMOS transistor 206 occurs. Due to the conflict, a short-circuit current IS1 flows through the PMOS transistors 201 and 203 and the NMOS transistor 205 or a short-circuit current IS2 flows through the PMOS transistors 202 and 204 and the NMOS transistor 206. The conventional level converting flip-flop 200 may consume a larger amount of electric power and have a pull-up speed and pull-down speed of a smaller output data signal.
A pull-up speed of the output data signal is determined according to a level of the output supply voltage VDDH and the sizes, e.g., channel lengths and widths, of the PMOS transistors 201, 202, 203, and 204. A pull-down speed of the output data signal is determined according to a level of the input supply voltage VDDL and the sizes, e.g., channel lengths and widths, of the NMOS transistors 205 and 206. A clock-to-output time may significantly change according to changes in the output supply voltage VDDH. The clock-to-output time if the output data signal rises to a high level, e.g., the output supply voltage VDDH, and the clock-to-output time if the output data signal falls to a low level, e.g., the input supply voltage VSS, change according to changes in the output supply voltage VDDH, and a duty ratio of the output data signal may significantly change. Accordingly, a propagation delay time of the conventional level converting flip-flop 200 may not be constant because of changes in the output supply voltage VDDH.